1. Field
This disclosure relates to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor devices having buried gate structures and methods of manufacturing the same.
2. Description of the Related Art
As the recent semiconductor devices tend to be downsized and high integrated, the pattern width has been reduced and the channel length has been shortened in a cell transistor. Thus, it has been getting more difficult to obtain a sufficient refresh time of memory devices due to the short channel effect.
A recess channel array transistor (RCAT) has been introduced for obtaining a sufficient effective channel length. However, the RCAT frequently fails by a high gate-induced drain leakage (GIDL). A buried channel array transistor (BCAT) has been proposed in such a way that the surface of the gate electrode is positioned below the surface of the silicon substrate to thereby minimize the GIDL of the RCAT.
Particularly, the word lines of the BCAT tend to be arranged in a 6F2 (F: minimum feature size) layout and the pitch of the word lines can be reduced to about 0.5F, the occupation area of each cell transistor can be remarkably reduced using this arrangement. Accordingly, both of the effective channel length and the chip size can be reduced in memory devices by using the BCAT.
However, the increase of the integration degree and the reduction of the occupation area tend to extremely reduce the area of the source/drain regions of the memory device, and thus in many cases the bit line contact and the storage node contact are electrically connected to each other.
Particularly, the isolation layer defining the drain region is likely to be removed from the substrate in an etching process for forming the contact hole in the drain region, thus the electrical insulation tends to be insufficient between the drain region and a neighboring source region. The insufficient electrical insulation between the drain region and the source region leads to the electrical short between the bit line contact and the storage node contact.
In addition, the gap distance between the neighboring source and drain regions may also be reduced due to the reduction of the occupation area, which makes it difficult to obtain a sufficient aligning margin when forming the bit line contact hole and the storage node contact hole.